`timescale 1ns / 1ps


module IM(
    input   wire        en,
    input   wire        clk,
    input   wire        rst,
    
    input   wire [31:0] i_addr,
    
    output  wire [31:0] o_inst
    );
    
    reg [7:0] mem [255:0];
    
    initial begin
        $readmemh("im.mem", mem);
    end
    
    wire [7:0] _addr;
    reg [31:0] t_inst;
    assign _addr = i_addr[7:0];
    assign o_inst = t_inst;
    
    always @(posedge clk) begin
        if (rst == 0) begin
            t_inst <= 0;
        end else begin
//            if (en == 1) begin
//                $display("aaa");
                t_inst <=
                    {mem[_addr + 3], mem[_addr + 2], mem[_addr + 1], mem[_addr]};
                $display(o_inst);
//            end
        end
    end
    
endmodule